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<section-title-en>2.6 Execution Contexts</section-title-en>
<section-title-ch>2.6 执行上下文</section-title-ch>
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	Application software targeting the 64-bit Intel architecture uses a variety of CPU registers to interact with the processor's features, shown in Figure 16 and Table 1. The values in these registers make up an application thread's state, or execution context.
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<p-ch>
	针对64位英特尔架构的应用软件使用各种CPU寄存器与处理器的功能进行交互，如图16和表1所示。这些寄存器中的值构成了一个应用线程的状态，或者说执行上下文。
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<img src="fig.16.jpg" />
<p-en>
	Figure 16: CPU registers in the 64-bit Intel architecture. RSP can be used as a general-purpose register (GPR), e.g., in pointer arithmetic, but it always points to the top of the program's stack. Segment registers are covered in §2.7.
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<p-ch>
	图16：64位Intel架构中的CPU寄存器。RSP可以作为通用寄存器(GPR)使用，例如，在指针运算中，但它总是指向程序的堆栈顶部。分段寄存器在§2.7中有所介绍。
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<p-en>
	OS kernels multiplex each logical processor (§2.9.4) between multiple software threads by context switching, namely saving the values of the registers that make up a thread's execution context, and replacing them with another thread's previously saved context. Context switching also plays a part in executing code inside secure containers, so its design has security implications.
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<p-ch>
	OS内核通过上下文切换在多个软件线程之间复用每个逻辑处理器（§2.9.4），即保存构成一个线程执行上下文的寄存器的值，并用另一个线程先前保存的上下文替换。在安全容器内执行代码时，上下文切换也起到了一定的作用，所以它的设计具有安全性。
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<p-en>
	Integers and memory addresses are stored in 16 general-purpose registers (GPRs). The first 8 GPRs have historical names: RAX, RBX, RCX, RDX, RSI, RDI, RSP, and RBP, because they are extended versions of the 32-bit Intel architecture's GPRs. The other 8 GPRs are simply known as R9-R16. RSP is designated for pointing to the top of the procedure call stack, which is simply referred to as the stack. RSP and the stack that it refers to are automatically read and modified by the CPU instructions that implement procedure calls, such as CALL and RET (return), and by specialized stack handling instructions such as PUSH and POP.
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<p-ch>
	整数和内存地址存储在16个通用寄存器（GPR）中。前8个GPR有历史名称。RAX、RBX、RCX、RDX、RSI、RDI、RSP和RBP，因为它们是32位英特尔架构GPR的扩展版本。其他8个GPR则简称为R9-R16。RSP被指定用于指向过程调用栈的顶部，简称为栈。RSP和它所指向的栈被实现过程调用的CPU指令（如CALL和RET（返回））和专门的栈处理指令（如PUSH和POP）自动读取和修改。
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<p-en>
	All applications also use the RIP register, which contains the address of the currently executing instruction, and the RFLAGS register, whose bits (e.g., the carry flag - CF) are individually used to store comparison results and control various instructions.
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<p-ch>
	所有的应用程序还使用RIP寄存器，其中包含当前执行指令的地址，以及RFLAGS寄存器，其位（如携带标志-CF）分别用于存储比较结果和控制各种指令。
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<p-en>
	Software might use other registers to interact with specific processor features, some of which are shown in Table 1.
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<p-ch>
	软件可能使用其他寄存器与特定的处理器功能进行交互，其中一些寄存器如表1所示。
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<img src="table.1.jpg" />
<p-en>
	Table 1: Sample feature-specific Intel architecture registers.
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<p-ch>
	表1：特定功能的英特尔架构寄存器样本。
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<p-en>
	The Intel architecture provides a future-proof method for an OS kernel to save the values of feature-specific registers used by an application. The XSAVE instruction takes in a requested-feature bitmap (RFBM), and writes the registers used by the features whose RFBM bits are set to 1 in a memory area. The memory area written by XSAVE can later be used by the XRSTOR instruction to load the saved values back into feature-specific registers. The memory area includes the RFBM given to XSAVE, so XRSTOR does not require an RFBM input.
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<p-ch>
	英特尔架构为操作系统内核提供了一种面向未来的方法，以保存应用程序使用的特定功能寄存器的值。XSAVE指令接收一个request-feature bitmap (RFBM)，并将RFBM位被设置为1的特性所使用的寄存器写入一个内存区域。XSAVE写入的内存区域以后可以被XRSTOR指令用来将保存的值加载回特征专用寄存器中。存储区包括给XSAVE的RFBM，所以XRSTOR不需要RFBM输入。
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<p-en>
	Application software declares the features that it plans to use to the kernel, so the kernel knows what XSAVE bitmap to use when context-switching. When receiving the system call, the kernel sets the XCR0 register to the feature bitmap declared by the application. The CPU generates a fault if application software attempts to use features that are not enabled by XCR0, so applications cannot modify feature-specific registers that the kernel wouldn't take into account when context-switching. The kernel can use the CPUID instruction to learn the size of the XSAVE memory area for a given feature bitmap, and compute how much memory it needs to allocate for the context of each of the application's threads.
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	应用软件向内核声明它计划使用的特征，这样内核就知道在上下文切换时要使用什么XSAVE位图。当接收到系统调用时，内核将XCR0寄存器设置为应用软件声明的特征位图。如果应用软件试图使用没有被XCR0启用的功能，CPU会产生故障，所以应用软件不能修改特定功能的寄存器，而内核在上下文切换时不会考虑这些寄存器。内核可以使用CPUID指令来了解给定特征位图的XSAVE内存区域的大小，并计算出需要为应用程序的每个线程的上下文分配多少内存。
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